Wire bonding, tape automated bonding (TAB) and flip chip bonding are popular packages for integrated circuits (ICs). Generally, wire bonding is used in low-density package with less than 300 inputs/outputs (I/Os). In high-density packages, up to 600 I/Os may be provided by TAB, and flip chip package provides much higher package density with more than 600 I/Os. In flip chip package, it is required to form bumps on the pads of the integrated circuit for the pressing process in chip-on-glass (COG), chip-on-board (COB), chip-on-film (COF), or other package processes. In order to reduce electrical noises and to increase adhesion and conductivity, gold is typically used for the bump material, which makes the bumping process expensive and difficult. Therefore, improving the bump structure and bumping process becomes an important issue. On the other hand, the density and performance of a package limit the size and performance of a chip. As the size of IC shrinks, the IC package becomes the bottleneck to further shrink the IC, if the density and performance of the package are not enhanced, for example the size and pitch of the bumps are limited or the conductivity of the bumps are not good enough.
FIG. 1 shows a conventional gold bump structure 10, in which on a substrate 12 a pad 14 is partially covered by a passivation layer 16, an under bump metallization (UBM) 18 is formed on the exposed surface of the pad 14 and the peripheral passivation layer 16, and a gold film 20 and bump 22 are formed on the UBM 18. Typically, the material of the pad 14 is aluminum, the passivation layer 16 comprises a layer of silicon dioxide 24 and a layer of silicon nitride 26, and the UBM 18 is a stacked layer of titanium and tungsten. The gold film 20 is sputtered and has denser crystalline, to increase the adhesion between the gold bump 22 and UBM 18. The gold bump 22 grows by electro-plating from the gold film 20 and has larger crystalline and higher hardness. Since the passivation layer 16 always has step 28 at the peripheral of the pad 14, the upper surface of the bump 22 will have step 30 at its edge and therefore, only the central concave region 32 becomes an effective region during the pressing process. The roughness h of the upper surface of the bump 22 is about 2 μm. If a larger effective region 32 is required, the pad 14 has to be larger. However, if only the width of the bump 22 is increased, as shown in FIG. 2, the effective region 32 will remain nearly the same because the increased region 34 on the upper surface of the bump 22 is useless due to the uneven upper surface of the bump 22. FIG. 3 shows several bumps 22 on the substrate 12, where the width of the pad 14 is w1, the bump gap is g, and the bump pitch is p. The width w2 of the bump 22 is no greater than the width w1 of the pad 14, so the effective region 32 is small compared to the pad 14. To increase the effective region 32, it is required to have a larger pad 14. However, the contact density of the chip is thus lowered and the chip size cannot be minimized. In addition, a larger pad 14 will result in a larger bump pitch p. If the bump gap g remains constant, the only way to obtain an increase in the contact density of the chip is to shrink the pad 14. But shrinking the pad 14 causes the minimization of the effective region 32. There's difficulty to solve this problem using conventional techniques.
A conventional bumping process is shown in FIGS. 4A to 4E. In FIG. 4A, a passivation layer 16 with a thickness of 1.2 μm is deposited to cover pads 14 on a substrate 12. In FIG. 4B, the passivation layer 16 is etched to form openings 36 to expose the pads 14, and after this step, the passivation layer 16 will have steps 38 at the peripherals of the pads 14. In particular, the thicker the passivation layer 16 is, the higher the steps 38 are and the deeper the openings 36 are. In FIG. 4C, Ti/W stack with a deposition thickness of 800 Å is used as UBM 18, and a gold film 20 with a thickness of 800 Å is deposited thereon. In this step, due to the step 38, step 40 formed thereon is even wider. The thicker the UBM 18 is, the narrower the concavity 42 is. FIG. 4D shows the structure after the UBM 18 and gold film 20 are patterned. In FIG. 4E, gold bumps 22 are grown up from the gold film 20 and have a thickness of about 17 μm. It is therefore shown by this process that the steps 38 are inevitable. As a result, effective regions 32 always have small areas. The thicker the UBM 18 is, the smaller the effective region 32 is. Moreover, the thicker the passivation layer 16 is, the greater the roughness h is. Even though the semiconductor process is capable to minimize the chip size, the backend package does not catch up with the IC shrinkage and thus limits the minimized size of the chip.
Further, a conventional bump structure has drawbacks during the pressing process. Referring to a COG structure 44 shown in FIG. 5, while pressing the bump 22 to a wire 48 on a glass substrate 46, an anisotropic conductive film (ACF) 50 is used therebetween as an interface. The ACF 50 is a polyimide (PI) with conductive particles thereof, and the conductive particles will form a conductive path in the pressing direction between the bump 22 and wire 48 during the pressing process. Since the surface roughness of the bump 22 is about 2 μm, the diameter of the conductive particles 52 within the ACF 50 has to be larger than 3 μm to construct an excellent conduction between the bump 22 and wire 48. However, if the conductive particles 52 are larger, then there will be fewer of them to be trapped in the effective region 32, and thus there's greater contact impedance and poor conduction quality after the pressing process. On the other hand, the conductive particles 56 with larger diameter inside the bump gap 34 will easily cause short or leakage between neighboring bumps 22, and thus lower the yield of the pressing process. If small conductive particles 52 are used, excellent connection between the bump 22 and wire 48 cannot be reached. Therefore, there's unbeatable difficulty in conventional technology. To satisfy the requirement of smaller size and higher I/O count of an IC chip, the pad 14 on the chip is required to be shrunk, and the effective region 32 is thus minimized, which causes the drop of the yield of the pressing process and conduction quality of the product. Furthermore, an elemental drawback of flip chip package is the weak mechanical strength at the peripheral region 58 of the bump 22, and damage happens easily due to lateral force. However, to obtain a smaller roughness h at the pressing surface of the bump 22 will have the step 28 to decrease, and a thinner passivation layer 16 could not overcome the drawbacks in weak mechanical strength.
Therefore, it is desired an improved bumping process and bump structure.